43 lines
827 B
Verilog
43 lines
827 B
Verilog
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module main;
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localparam width = 8;
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reg clk;
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reg [1:0] addr;
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logic [width-1:0] data [0:3];
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reg [width-1:0] Q;
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// Does SystemVerilog support continuous assignment
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// of unpacked arrays? I think it does, but the LRM
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// is really not clear on this.
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wire [width-1:0] data_x[0:3];
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assign data_x = data;
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always @(posedge clk)
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Q <= data_x[addr];
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reg [2:0] idx;
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initial begin
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clk = 0;
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data[0] = 0;
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data[1] = 1;
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data[2] = 2;
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data[3] = 3;
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addr = 0;
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for (idx = 0 ; idx < 4 ; idx += 1) begin
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clk = 0;
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#1 addr = idx[1:0];
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#1 clk = 1;
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#1 if (Q !== data[addr]) begin
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$display("FAILED -- data[%0d]==%h, Q==%h", addr, data[addr], Q);
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$finish;
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end
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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