58 lines
806 B
Verilog
58 lines
806 B
Verilog
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module test
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(input clk,
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input wire [7:0] D,
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input wire [1:0] S,
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output reg [7:0] Q [0:3]
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/* */);
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always @(posedge clk)
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Q[S] <= D;
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endmodule // test
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module main;
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reg clk;
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reg [1:0] S;
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reg [7:0] D;
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wire [7:0] Q [0:3];
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test dut(.clk(clk), .D(D), .S(S), .Q(Q));
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initial begin
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clk = 0;
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S = 0;
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D = 0;
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#1 clk = 1;
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#1 clk = 0;
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S = 1;
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D = 1;
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#1 clk = 1;
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#1 clk = 0;
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S = 2;
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D = 2;
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#1 clk = 1;
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#1 clk = 0;
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S = 3;
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D = 3;
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#1 clk = 1;
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#1 clk = 0;
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for (int idx = 0 ; idx < 4 ; idx = idx+1) begin
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if (Q[idx] != idx) begin
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$display("FAILED -- Q[%0d] = %0d", idx, Q[idx]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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