53 lines
960 B
Verilog
53 lines
960 B
Verilog
int num1 = 101; string str1 = "unit1";
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int num2 = 102; string str2 = "unit1";
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int num3 = 103; string str3 = "unit1";
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class c1;
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int num2 = 100; string str2 = "c1";
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task display;
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begin
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$display("%d from %s", num1, str1);
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$display("%d from %s", num2, str2);
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end
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endtask
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endclass
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module m1();
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int num2 = 112; string str2 = "m1";
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c1 obj;
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initial begin
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#1;
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obj = new;
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obj.display;
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$display("%d from %s", num1, str1);
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$display("%d from %s", num2, str2);
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$display("%d from %s", num3, str3);
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$display("%d from %s", m2.num4, m2.str4);
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end
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/* This should not change the result, but Icarus ignores the order in
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which variables are declared and used.
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int num3 = 113; string str3 = "m1";
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*/
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endmodule
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module m2();
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int num1 = 121; string str1 = "m2";
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int num2 = 122; string str2 = "m2";
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int num3 = 123; string str3 = "m2";
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int num4 = 124; string str4 = "m2";
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m1 m1inst();
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endmodule
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