155 lines
2.9 KiB
Verilog
155 lines
2.9 KiB
Verilog
timeunit 10us / 10us;
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module fast_g (out);
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output out;
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reg out;
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initial begin
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#0 out = 0;
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#1 out = 1; // 10us
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end
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endmodule // fast_g
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`timescale 100us / 1us
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// These will be ignored since a `timescale was already given.
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timeunit 10us/10us;
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module slow (out);
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output out;
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reg out;
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initial begin
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#0 out = 0;
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#1 out = 1; // 100us
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end
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endmodule // slow
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module fast (out);
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timeunit 10us/1us;
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output out;
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reg out;
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initial begin
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#0 out = 0;
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#1 out = 1; // 10us
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end
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endmodule // fast
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module saf(out);
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output out;
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reg out;
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initial begin
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#0 out = 0;
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#1 out = 1; // 100us
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end
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endmodule // saf
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`timescale 1us / 1us
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module main;
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reg pass;
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wire slow, fast, fast_g, saf;
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slow m1 (slow);
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fast_g m2 (fast_g);
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fast m3 (fast);
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saf m4 (saf);
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initial begin
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pass = 1'b1;
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#9;
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if (slow !== 1'b0) begin
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$display("FAILED: slow at 9us, expected 1'b0, got %b.", slow);
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pass = 1'b0;
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end
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if (saf !== 1'b0) begin
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$display("FAILED: saf at 9us, expected 1'b0, got %b.", saf);
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pass = 1'b0;
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end
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if (fast !== 1'b0) begin
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$display("FAILED: fast at 9us, expected 1'b0, got %b.", fast);
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pass = 1'b0;
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end
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if (fast_g !== 1'b0) begin
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$display("FAILED: fast_g at 9us, expected 1'b0, got %b.", fast_g);
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pass = 1'b0;
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end
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#2 // 11us
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if (slow !== 1'b0) begin
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$display("FAILED: slow at 11us, expected 1'b0, got %b.", slow);
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pass = 1'b0;
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end
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if (saf !== 1'b0) begin
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$display("FAILED: saf at 11us, expected 1'b0, got %b.", saf);
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pass = 1'b0;
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end
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if (fast !== 1'b1) begin
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$display("FAILED: fast at 11us, expected 1'b1, got %b.", fast);
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pass = 1'b0;
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end
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if (fast_g !== 1'b1) begin
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$display("FAILED: fast_g at 11us, expected 1'b1, got %b.", fast_g);
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pass = 1'b0;
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end
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#88 // 99 us
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if (slow !== 1'b0) begin
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$display("FAILED: slow at 99us, expected 1'b0, got %b.", slow);
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pass = 1'b0;
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end
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if (saf !== 1'b0) begin
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$display("FAILED: saf at 99us, expected 1'b0, got %b.", saf);
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pass = 1'b0;
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end
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if (fast !== 1'b1) begin
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$display("FAILED: fast at 99us, expected 1'b1, got %b.", fast);
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pass = 1'b0;
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end
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if (fast_g !== 1'b1) begin
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$display("FAILED: fast_g at 99us, expected 1'b1, got %b.", fast_g);
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pass = 1'b0;
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end
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#2 // 101 us
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if (slow !== 1'b1) begin
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$display("FAILED: slow at 101us, expected 1'b1, got %b.", slow);
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pass = 1'b0;
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end
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if (saf !== 1'b1) begin
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$display("FAILED: saf at 101us, expected 1'b1, got %b.", saf);
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pass = 1'b0;
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end
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if (fast !== 1'b1) begin
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$display("FAILED: fast at 101us, expected 1'b1, got %b.", fast);
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pass = 1'b0;
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end
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if (fast_g !== 1'b1) begin
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$display("FAILED: fast_g at 101us, expected 1'b1, got %b.", fast_g);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end // initial begin
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endmodule // main
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