20 lines
370 B
Verilog
20 lines
370 B
Verilog
module top;
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typedef reg [4:0] T1;
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typedef T1 [7:0] T2;
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int bound = 2;
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T2 q_vec [$];
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T2 q_vec1 [$:-1];
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T2 q_vec2 [$:'X];
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T2 q_vec3 [$:bound];
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initial begin
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$display(q_vec.size(1));
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$display(q_vec.pop_front(1));
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$display(q_vec.pop_back(1));
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q_vec.push_front(1, 2);
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q_vec.push_back(1, 2);
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$display("FAILED");
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end
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endmodule : top
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