81 lines
2.3 KiB
Verilog
81 lines
2.3 KiB
Verilog
module top;
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typedef reg [4:0] T1;
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typedef T1 [7:0] T2;
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T2 q_tst [$:2];
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T2 q_tmp [$];
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bit passed;
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task automatic check_size(integer size,
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string fname,
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integer lineno);
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if (q_tst.size !== size) begin
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$display("%s:%0d: Failed: queue size != %0d (%0d)",
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fname, lineno, size, q_tst.size);
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passed = 1'b0;
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end
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endtask
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task automatic check_idx_value(integer idx,
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T2 expected,
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string fname,
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integer lineno);
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if (q_tst[idx] != expected) begin
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$display("%s:%0d: Failed: element [%0d] != %0d (%0d)",
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fname, lineno, idx, expected, q_tst[idx]);
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passed = 1'b0;
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end
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endtask
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initial begin
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passed = 1'b1;
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check_size(0, `__FILE__, `__LINE__);
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q_tst.push_back(2);
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q_tst.push_front(1);
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q_tst.push_back(3);
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q_tst.push_back(100); // Warning: item not added.
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check_size(3, `__FILE__, `__LINE__);
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check_idx_value(0, 1, `__FILE__, `__LINE__);
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check_idx_value(1, 2, `__FILE__, `__LINE__);
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check_idx_value(2, 3, `__FILE__, `__LINE__);
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q_tst.push_front(5); // Warning: back item removed.
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q_tst[3] = 3; // Warning: item not added.
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check_size(3, `__FILE__, `__LINE__);
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check_idx_value(0, 5, `__FILE__, `__LINE__);
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check_idx_value(1, 1, `__FILE__, `__LINE__);
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check_idx_value(2, 2, `__FILE__, `__LINE__);
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q_tst.insert(3, 10); // Warning: item not added.
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q_tst.insert(1, 2); // Warning: back item removed.
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check_size(3, `__FILE__, `__LINE__);
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check_idx_value(0, 5, `__FILE__, `__LINE__);
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check_idx_value(1, 2, `__FILE__, `__LINE__);
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check_idx_value(2, 1, `__FILE__, `__LINE__);
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q_tst = '{1, 2, 3, 4}; // Warning: items not added.
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check_size(3, `__FILE__, `__LINE__);
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check_idx_value(0, 1, `__FILE__, `__LINE__);
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check_idx_value(1, 2, `__FILE__, `__LINE__);
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check_idx_value(2, 3, `__FILE__, `__LINE__);
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q_tmp = '{4, 3, 2, 1};
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q_tst = q_tmp; // Warning not all items copied
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q_tmp[0] = 5;
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check_size(3, `__FILE__, `__LINE__);
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check_idx_value(0, 4, `__FILE__, `__LINE__);
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check_idx_value(1, 3, `__FILE__, `__LINE__);
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check_idx_value(2, 2, `__FILE__, `__LINE__);
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if (passed) $display("PASSED");
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end
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endmodule : top
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