100 lines
2.2 KiB
Verilog
100 lines
2.2 KiB
Verilog
// Check that the signedness of the element type of a queue is correctly handled
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// whenn calling one of the pop methods with parenthesis.
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module test;
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bit failed = 1'b0;
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`define check(x) \
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if (!(x)) begin \
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$display("FAILED(%0d): ", `__LINE__, `"x`"); \
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failed = 1'b1; \
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end
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int unsigned x = 10;
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int y = 10;
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int z;
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longint w;
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shortint qs[$];
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bit [15:0] qu[$];
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initial begin
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for (int i = 0; i < 16; i++) begin
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qu.push_back(-1);
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qs.push_back(-1);
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end
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// These all evaluate as signed
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`check($signed(qu.pop_back) < 0)
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`check(qs.pop_back < 0)
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`check($signed(qu.pop_front) < 0)
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`check(qs.pop_front < 0)
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// These all evaluate as unsigned
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`check(qu.pop_back > 0)
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`check({qs.pop_back} > 0)
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`check($unsigned(qs.pop_back) > 0)
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`check(qs.pop_back > 16'h0)
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`check(qu.pop_front > 0)
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`check({qs.pop_front} > 0)
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`check($unsigned(qs.pop_front) > 0)
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`check(qs.pop_front > 16'h0)
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// In arithmetic expressions if one operand is unsigned all operands are
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// considered unsigned
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z = qu.pop_back + x;
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`check(z === 65545)
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z = qu.pop_back + y;
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`check(z === 65545)
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z = qu.pop_front + x;
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`check(z === 65545)
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z = qu.pop_front + y;
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`check(z === 65545)
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z = qs.pop_back + x;
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`check(z === 65545)
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z = qs.pop_back + y;
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`check(z === 9)
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z = qs.pop_front + x;
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`check(z === 65545)
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z = qs.pop_front + y;
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`check(z === 9)
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// For ternary operators if one operand is unsigned the result is unsigend
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z = x ? qu.pop_back : x;
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`check(z === 65535)
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z = x ? qu.pop_back : y;
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`check(z === 65535)
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z = x ? qu.pop_front : x;
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`check(z === 65535)
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z = x ? qu.pop_front : y;
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`check(z === 65535)
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z = x ? qs.pop_back : x;
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`check(z === 65535)
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z = x ? qs.pop_back : y;
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`check(z === -1)
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z = x ? qs.pop_front : x;
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`check(z === 65535)
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z = x ? qs.pop_front : y;
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`check(z === -1)
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// Size return value is always positive, but check that it gets padded
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// properly
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w = x ? qu.size : 64'h123;
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`check(w === 64'h4)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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