46 lines
786 B
Verilog
46 lines
786 B
Verilog
// Check that queues with compatible packed base types can be passed as task
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// arguments. Even it the element types are not identical.
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module test;
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typedef logic [31:0] T[$];
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task t1(logic [31:0] q[$]);
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q[0] = 1;
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endtask
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task t2(logic [7:0][3:0] q[$]);
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q[0] = 1;
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endtask
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task t3([31:0] q[$]);
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q[0] = 1;
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endtask
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task t4(T q);
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q[0] = 1;
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endtask
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// For two packed types to be compatible they need to have the same packed
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// width, both be 2-state or 4-state and both be either signed or unsigned.
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logic [31:0] q1[$];
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logic [7:0][3:0] q2[$];
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initial begin
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q1.push_back(1);
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q2.push_back(2);
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t1(q1);
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t1(q2);
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t2(q1);
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t2(q2);
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t3(q1);
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t3(q2);
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t4(q1);
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t4(q2);
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$display("PASSED");
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end
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endmodule
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