28 lines
569 B
Verilog
28 lines
569 B
Verilog
// Check that queues with compatible packed base types can be assigned to each
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// other. Even if the element types are not identical.
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module test;
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typedef bit [31:0] T1;
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typedef bit [31:0] T2[$];
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// For two packed types to be compatible they need to have the same packed
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// width, both be 2-state or 4-state and both be either signed or unsigned.
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bit [32:1] q1[$];
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bit [7:0][3:0] q2[$];
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int unsigned q3[$];
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T1 q4[$];
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T2 q5;
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initial begin
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q2 = q1;
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q3 = q2;
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q4 = q3;
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q5 = q4;
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q1 = q5;
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$display("PASSED");
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end
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endmodule
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