31 lines
588 B
Verilog
31 lines
588 B
Verilog
// Check that it is possible to reference a package scoped function, even if
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// there is a type identifier of the same name in the current scope.
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bit failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \
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failed = 1'b1; \
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end
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package P;
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function integer T(integer x);
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return x + 1;
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endfunction
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endpackage
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module test;
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typedef integer T;
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initial begin
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integer x;
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x = P::T(10);
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`check(x, 11)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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