39 lines
891 B
Verilog
39 lines
891 B
Verilog
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// This tests the basic support for default arguments to task/function
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// ports. The default port syntax gives SystemVerilog a limited form
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// of variable argument lists.
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program main;
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class foo_t;
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int int_val;
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logic[3:0]log_val;
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function new (int int_init, logic[3:0] log_init = 4'bzzzz);
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int_val = int_init;
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log_val = log_init;
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endfunction : new
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endclass : foo_t
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foo_t obj1;
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initial begin
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obj1 = new (5, 4'b1010);
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if (obj1.int_val != 5 || obj1.log_val !== 4'b1010) begin
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$display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val);
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$finish;
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end
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obj1 = new (7);
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if (obj1.int_val != 7 || obj1.log_val !== 4'bzzzz) begin
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$display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val);
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$finish;
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end
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$display("PASSED");
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end
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endprogram // main
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