45 lines
661 B
Verilog
45 lines
661 B
Verilog
// Test default value for output port
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// This should work, but isn't supported yet
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module test();
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integer a;
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integer b;
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integer c;
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task k(input integer i = a, output integer j = b);
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j = i;
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endtask
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integer result;
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reg fail = 0;
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initial begin
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a = 1;
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b = 2;
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k(3,c);
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$display(a,,b,,c);
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if (a !== 1 || b !== 2 || c !== 3) fail = 1;
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k(,c);
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$display(a,,b,,c);
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if (a !== 1 || b !== 2 || c !== 1) fail = 1;
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k(4,);
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$display(a,,b,,c);
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if (a !== 1 || b !== 4 || c !== 1) fail = 1;
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k();
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$display(a,,b,,c);
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if (a !== 1 || b !== 1 || c !== 1) fail = 1;
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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