48 lines
622 B
Verilog
48 lines
622 B
Verilog
// Test non-constant port default value.
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module test();
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integer a;
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integer b;
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function integer k(integer i, integer j = a+b);
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k = i + j;
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endfunction
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wire [31:0] x = k(1);
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wire [31:0] y = k(2);
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integer result;
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reg fail = 0;
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initial begin
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a = 1;
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b = 2;
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#0;
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result = x;
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$display(result);
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if (result !== 4) fail = 1;
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result = y;
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$display(result);
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if (result !== 5) fail = 1;
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result = k(3);
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$display(result);
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if (result !== 6) fail = 1;
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result = k(3,4);
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$display(result);
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if (result !== 7) fail = 1;
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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