36 lines
796 B
Verilog
36 lines
796 B
Verilog
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// This tests the basic support for default arguments to task/function
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// ports. The default port syntax gives SystemVerilog a limited form
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// of variable argument lists.
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program main;
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task increment(output int res, input int val, input int step = 1, input int flag = 1);
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res = val + step*flag;
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endtask // increment
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int res;
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initial begin
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increment(res,5);
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if (res !== 6) begin
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$display("FAILED -- increment(5) --> %0d", res);
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$finish;
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end
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increment(res,5,2);
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if (res !== 7) begin
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$display("FAILED -- increment(5,2) --> %0d", res);
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$finish;
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end
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increment(res,5,,3);
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if (res !== 8) begin
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$display("FAILED -- increment(5,,3) --> %0d", res);
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$finish;
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end
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$display("PASSED");
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end
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endprogram // main
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