32 lines
755 B
Verilog
32 lines
755 B
Verilog
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// This tests the basic support for default arguments to task/function
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// ports. The default port syntax gives SystemVerilog a limited form
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// of variable argument lists.
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program main;
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function int increment(int val, int step = 1, int flag = 1);
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increment = val + step*flag;
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endfunction // increment
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initial begin
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if (increment(5) !== 6) begin
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$display("FAILED -- increment(5) --> %0d", increment(5));
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$finish;
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end
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if (increment(5,2) !== 7) begin
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$display("FAILED -- increment(5,2) --> %0d", increment(5,2));
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$finish;
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end
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if (increment(5,,3) !== 8) begin
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$display("FAILED -- increment(5,,3) --> %0d", increment(5,,3));
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$finish;
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end
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$display("PASSED");
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end
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endprogram // main
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