32 lines
494 B
Verilog
32 lines
494 B
Verilog
package p_defs;
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class a_class;
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int id_;
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function new(int id);
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id_ = id;
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endfunction
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task display();
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$display("This is class %0d.", id_);
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endtask
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endclass
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endpackage
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// This should print the following:
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// This is class 2.
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// This is class 1.
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module top;
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import p_defs::a_class;
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a_class ac1;
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a_class ac2;
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initial begin
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ac1 = new(1);
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ac2 = new(2);
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ac2.display();
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ac1.display();
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end
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endmodule
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