34 lines
651 B
Verilog
34 lines
651 B
Verilog
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module main;
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typedef struct packed {
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logic [3:0] adr;
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logic [3:0] val;
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} foo_s;
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foo_s [3:0][1:0] ival;
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foo_s [3:0][1:0] oval;
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genvar g;
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for (g = 0 ; g < 4 ; g = g+1) begin:loop
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TEST dut(.in(ival[g][0]),
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.out(oval[g][0]));
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end
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initial begin
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ival = 'hx3x2x1x0;
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#1 $display("ival = %h, oval = %h", ival, oval);
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if (oval !== 64'hzzxxzzxxzzxdzzxf) begin
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$display("FAILED -- oval=%h", oval);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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module TEST (input wire [7:0] in, output wire [7:0] out);
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assign out = ~in;
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endmodule // TEST
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