42 lines
747 B
Verilog
42 lines
747 B
Verilog
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// This tests SystemVerilog packages. Make sure that typedef
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// names work.
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package p1;
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typedef struct packed {
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bit [7:0] high;
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bit [7:0] low;
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} word_t;
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word_t word;
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endpackage
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module main;
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import p1::word;
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initial begin
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if ($bits(word) != 16) begin
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$display("FAILED -- $bits(p1::word) == %0d", $bits(p1::word));
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$finish;
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end
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word = 'haa55;
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if (word != 'haa55) begin
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$display("FAILED -- p1::word = %h", word);
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$finish;
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end
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word.low = 'h66;
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word.high = 'hbb;
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if (word != 'hbb66 || word.low != 8'h66) begin
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$display("FAILED -- p1::word = %h", word);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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