35 lines
597 B
Verilog
35 lines
597 B
Verilog
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// This tests SystemVerilog packages. Make sure that typedef
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// names work.
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package p1;
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typedef struct packed {
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bit [7:0] high;
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bit [7:0] low;
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} word_t;
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endpackage
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program main;
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import p1::word_t;
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word_t word;
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initial begin
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if ($bits(word) != 16) begin
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$display("FAILED -- $bits(word) == %0d", $bits(word));
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$finish;
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end
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word.low = 'h55;
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word.high = 'haa;
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if (word != 'haa55) begin
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$display("FAILED -- word = %h", word);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endprogram // main
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