19 lines
623 B
Verilog
19 lines
623 B
Verilog
module test();
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integer i = 1;
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initial begin
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assume(i == 1);
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assume(i == 0);
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assume(i == 1) else $display("Check 3 : this shouldn't be displayed");
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assume(i == 0) else $display("Check 4 : this should be displayed");
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assume(i == 1) $display("Check 5 : this should be displayed");
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assume(i == 0) $display("Check 6 : this shouldn't be displayed");
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assume(i == 1) $display("Check 7 : this should be displayed");
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else $display("Check 7 : this shouldn't be displayed");
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assume(i == 0) $display("Check 8 : this shouldn't be displayed");
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else $display("Check 8 : this should be displayed");
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end
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endmodule
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