37 lines
820 B
Verilog
37 lines
820 B
Verilog
module test();
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reg [3:0] array[0:1][0:2];
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reg [3:0] expected;
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reg failed = 0;
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initial begin
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 3; j++) begin
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array[i][j] = i * 4 + j;
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end
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end
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foreach (array[i,j,k]) begin
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expected = i * 4 + j;
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$display("Value of array[%0d][%0d][%0d]=%b", i, j, k, array[i][j][k]);
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if (array[i][j][k] !== expected[k]) failed = 1;
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end
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foreach (array[i,j]) begin
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expected = i * 4 + j;
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$display("Value of array[%0d][%0d]=%h", i, j, array[i][j]);
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if (array[i][j] !== expected) failed = 1;
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end
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foreach (array[i]) begin
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expected = i * 4;
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$display("Value of array[%0d][0]=%h", i, array[i][0]);
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if (array[i][0] !== expected) failed = 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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