73 lines
1.9 KiB
Verilog
73 lines
1.9 KiB
Verilog
/*
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* Copyright (c) 2014 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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`default_nettype none
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module main;
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class test_t;
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reg [1:0] a;
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reg [2:0] b;
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function new (int ax, int bx);
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begin
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a = ax;
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b = bx;
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end
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endfunction // new
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endclass // test_t
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test_t foo [0:3][0:7], tmp;
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bit [3:0] idx1, idx2;
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initial begin
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for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
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for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
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foo[idx1][idx2] = new(idx1,idx2);
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end
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foreach (foo[ia,ib]) begin
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if (ia > 3 || ib > 7) begin
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$display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
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$finish;
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end
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tmp = foo[ia][ib];
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if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
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$display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
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$finish;
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end
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foo[ia][ib] = null;
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end
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for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
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for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
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if (foo[idx1][idx2] != null) begin
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$display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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