27 lines
455 B
Verilog
27 lines
455 B
Verilog
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program main;
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int sum;
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logic idx; // Use this to test scope;
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initial begin
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sum = 0;
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idx = 1'bx;
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for (int idx = 0 ; idx < 8 ; idx += 1) begin
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sum += idx;
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end
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if (sum != 28) begin
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$display("FAILED -- sum=%0d", sum);
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$finish;
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end
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if (idx !== 1'bx) begin
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$display("FAILED -- idx in upper scope became %b", idx);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endprogram
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