43 lines
773 B
Verilog
43 lines
773 B
Verilog
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module foo_mod(output reg pass_flag, input wire go_flag);
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typedef enum logic [1:0] { W0, W1, W2 } foo_t;
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foo_t foo;
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always @(posedge go_flag) begin
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pass_flag = 0;
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if ($bits(foo) !== 2) begin
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$display("FAILED -- $bits(foo)=%0d", $bits(foo));
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$finish;
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end
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if ($bits(foo_t) !== 2) begin
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$display("FAILED -- $bits(foo_t)=%0d", $bits(foo_t));
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$finish;
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end
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pass_flag = 1;
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end
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endmodule
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module main;
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logic go_flag = 0;
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wire [1:0] pass_flag;
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foo_mod dut[1:0] (.pass_flag(pass_flag), .go_flag(go_flag));
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initial begin
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#1 go_flag = 1;
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#1 if (pass_flag !== 2'b11) begin
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$display("FAILED -- pass_flag=%b", pass_flag);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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