62 lines
1.8 KiB
Verilog
62 lines
1.8 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Tests if dynamic array words are of appropriate size.
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module sv_cast_string();
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bit [6:1] darr [];
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bit [63:0] darr_64 [];
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logic [4:10] darr_rev [];
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initial begin
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darr = new[4];
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darr_64 = new[8];
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darr_rev = new[3];
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if($size(darr[0]) != 6 || $size(darr_64[2]) != 64 || $size(darr_rev[1]) != 7 ||
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$size(darr) != 4 || $size(darr_64) != 8 || $size(darr_rev) != 3)
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begin
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$display("FAILED");
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$finish();
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end
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darr[0] = 6'b110011;
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darr[1] = 6'b000011;
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darr[2] = darr[0] + darr[1];
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darr_64[0] = 64'hcafe0000dead0000;
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darr_64[1] = 64'h0000bad00000d00d;
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darr_64[2] = darr_64[0] + darr_64[1];
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darr_rev[0] = 7'b1111000;
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darr_rev[1] = 7'b0000011;
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darr_rev[2] = darr_rev[0] + darr_rev[1];
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if(darr[2] !== 6'b110110 || darr_64[2] !== 64'hcafebad0deadd00d ||
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darr_rev[2] !== 7'b1111011)
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begin
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$display("FAILED");
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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