33 lines
596 B
Verilog
33 lines
596 B
Verilog
module main;
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bit pass;
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bit signed [7:0] s8[];
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bit [7:0] u8[];
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string res, fmt;
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initial begin
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pass = 1'b1;
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s8 = new[2];
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u8 = new[2];
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s8[0] = -1;
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u8[0] = -1;
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fmt = "%0d";
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$display(fmt, s8[0]);
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$sformat(res, fmt, s8[0]);
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if (res != "-1") begin
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$display("Failed: expected '-1', got '%s'", res);
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pass = 1'b0;
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end
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$display(fmt, u8[0]);
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$swrite(res, u8[0]);
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if (res != "255") begin
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$display("Failed: expected '255', got '%s'", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule // main
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