19 lines
341 B
Verilog
19 lines
341 B
Verilog
// Check that out-of-bounds access on a 2-state vector dynamic array works and
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// returns the correct value.
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module test;
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bit [7:0] d[];
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logic [7:0] x;
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initial begin
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x = d[1];
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if (x === 8'h00) begin
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$display("PASSED");
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end else begin
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$display("FAILED. Expected 00000000, got %b",x);
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end
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end
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endmodule
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