19 lines
318 B
Verilog
19 lines
318 B
Verilog
// Check that out-of-bounds access on a real typed dynamic array works and
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// returns the correct value.
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module test;
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real d[];
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real x;
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initial begin
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x = d[1];
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if (x == 0.0) begin
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$display("PASSED");
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end else begin
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$display("FAILED. Expected 0.0, got %f", x);
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end
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end
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endmodule
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