45 lines
779 B
Verilog
45 lines
779 B
Verilog
// Check that dynamic arrays with compatible packed base types can be passed as
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// task arguments. Even it the element types are not identical.
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module test;
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typedef logic [31:0] T[];
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task t1(logic [31:0] d[]);
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d[0] = 1;
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endtask
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task t2(logic [7:0][3:0] d[]);
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d[0] = 1;
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endtask
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task t3([31:0] d[]);
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d[0] = 1;
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endtask
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task t4(T d);
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d[0] = 1;
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endtask
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// For two packed types to be compatible they need to have the same packed
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// width, both be 2-state or 4-state and both be either signed or unsigned.
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logic [31:0] d1[];
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logic [7:0][3:0] d2[];
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initial begin
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d1 = new[1];
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d2 = new[1];
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t1(d1);
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t1(d2);
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t2(d1);
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t2(d2);
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t3(d1);
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t3(d2);
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t4(d1);
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t4(d2);
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$display("PASSED");
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end
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endmodule
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