34 lines
673 B
Verilog
34 lines
673 B
Verilog
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program main;
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function int sum_array(bit[7:0] array[]);
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int idx;
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sum_array = 0;
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for (idx = 0 ; idx < array.size() ; idx = idx+1)
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sum_array += array[idx];
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endfunction // sum_array
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bit [7:0] obj[];
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int foo;
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initial begin
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foo = sum_array('{});
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if (foo !== 0) begin
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$display("FAILED -- sum of empty array returns %0d", foo);
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$finish;
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end
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obj = new[3];
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obj[0] = 1;
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obj[1] = 2;
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obj[2] = 3;
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foo = sum_array(obj);
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if (foo !== 6) begin
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$display("FAILED -- sum of '{1,2,3} is %0d", foo);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endprogram // main
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