58 lines
1.2 KiB
Verilog
58 lines
1.2 KiB
Verilog
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/*
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* This demonstrates a basic dynamic array
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*/
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module main;
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string foo[];
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int idx;
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string tmp;
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initial begin
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if (foo.size() != 0) begin
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$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
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$finish;
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end
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foo = new[10];
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if (foo.size() != 10) begin
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$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
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$finish;
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end
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tmp = "fooa";
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for (idx = 0 ; idx < foo.size() ; idx += 1) begin
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tmp[3] = 'h41 + idx;
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foo[idx] = tmp;
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end
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$display("foo[7] = %0s", foo[7]);
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if (foo[7] != "fooH") begin
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$display("FAILED -- foo[7] = %0s (s.b. fooH)", foo[7]);
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$finish;
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end
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$display("foo[9] = %0s", foo[9]);
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if (foo[9] != "fooJ") begin
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$display("FAILED -- foo[9] = %0s (s.b. fooJ)", foo[9]);
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$finish;
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end
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for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
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tmp[3] = 'h41 + (idx%10);
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if (foo[idx%10] != tmp) begin
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$display("FAILED -- foo[%0d%%10] = %0s", idx, foo[idx%10]);
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$finish;
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end
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end
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foo.delete();
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if (foo.size() != 0) begin
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$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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