67 lines
1.2 KiB
Verilog
67 lines
1.2 KiB
Verilog
// Check that the signedness of class properties are handled correctly when
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// accessing the property on a class object.
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module test;
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bit failed = 1'b0;
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`define check(x) \
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if (!(x)) begin \
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$display("FAILED(%0d): ", `__LINE__, `"x`"); \
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failed = 1'b1; \
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end
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class C;
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shortint s = -1;
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bit [15:0] u = -1;
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endclass
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C c;
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int unsigned x = 10;
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int y = 10;
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int z;
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initial begin
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c = new;
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// These all evaluate as signed
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`check(c.s < 0)
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`check($signed(c.u) < 0)
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// These all evaluate as unsigned
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`check(c.u > 0)
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`check({c.s} > 0)
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`check($unsigned(c.s) > 0)
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`check(c.s > 16'h0)
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// In arithmetic expressions if one operand is unsigned all operands are
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// considered unsigned
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z = c.u + x;
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`check(z === 65545)
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z = c.u + y;
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`check(z === 65545)
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z = c.s + x;
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`check(z === 65545)
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z = c.s + y;
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`check(z === 9)
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// For ternary operators if one operand is unsigned the result is unsigend
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z = x ? c.u : x;
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`check(z === 65535)
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z = x ? c.u : y;
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`check(z === 65535)
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z = x ? c.s : x;
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`check(z === 65535)
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z = x ? c.s : y;
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`check(z === -1)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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