55 lines
966 B
Verilog
55 lines
966 B
Verilog
// Check that default values on task methods are supported and it is possible to
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// omit any of the arguments.
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class C;
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integer r;
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task t(integer x = 1, integer y = 2, integer z = 3);
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r = x + y + z;
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endtask
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endclass
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module test;
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C c = new;
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bit failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED. %s, expected %0d, got %0d", `"expr`", val, expr); \
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failed = 1'b1; \
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end
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initial begin
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c.t();
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`check(c.r, 6);
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c.t(4);
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`check(c.r, 9);
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c.t(4, );
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`check(c.r, 9);
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c.t(4, ,);
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`check(c.r, 9);
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c.t(4, 6);
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`check(c.r, 13);
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c.t(4, 6, );
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`check(c.r, 13);
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c.t(4, , 8);
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`check(c.r, 14);
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c.t(4, 6, 8);
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`check(c.r, 18);
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c.t(, 6);
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`check(c.r, 10);
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c.t(, 6, );
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`check(c.r, 10);
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c.t(, 6, 8);
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`check(c.r, 15);
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c.t(, , 8);
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`check(c.r, 11);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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