39 lines
847 B
Verilog
39 lines
847 B
Verilog
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/*
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* This tests a trivial class. This tests that properties can be
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* given types, and that the types behave properly.
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*/
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program main;
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// Trivial example of a class
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class foo_t ;
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shortint signed a;
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shortint unsigned b;
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endclass : foo_t // foo_t
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foo_t obj;
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initial begin
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obj = new;
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// This is the most trivial assignment of class properties.
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obj.a = 'hf_ffff;
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obj.b = 'hf_ffff;
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if (obj.a != -1 || obj.b != 65535) begin
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$display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
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$finish;
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end
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obj.a = obj.a + 1;
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obj.b = obj.b + 1;
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if (obj.a != 0 || obj.b != 0) begin
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$display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endprogram // main
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