47 lines
845 B
Verilog
47 lines
845 B
Verilog
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/*
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* This tests a trivial class. This tests that properties can be
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* given types, and that the types behave properly.
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*/
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program main;
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class bar_t;
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int a;
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int b;
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endclass // bar_t
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// Trivial example of a class
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class foo_t ;
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byte a;
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bar_t b;
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endclass : foo_t // foo_t
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foo_t obj;
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bar_t tmp;
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initial begin
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obj = new;
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// This is the most trivial assignment of class properties.
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obj.a = 'hf_ff;
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obj.b = new;
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tmp = obj.b;
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tmp.a = 0;
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tmp.b = 1;
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if (obj.a != -1) begin
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$display("FAILED -- assign to object: obj.a=%0d", obj.a);
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$finish;
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end
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if (tmp.a != 0 || tmp.b != 1) begin
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$display("FAILED -- obj.b.a=%0d, obj.b.b=%0d", tmp.a, tmp.b);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endprogram // main
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