57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test for casting a string to a vector type.
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module sv_cast_string();
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string str;
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typedef logic [55:0] strbits;
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strbits chars;
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initial begin
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int i;
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str = "0123456";
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chars = strbits'(str);
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if(chars != 56'h30313233343536)
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begin
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$display("FAILED 1 chars = %x", chars);
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$finish();
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end
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str = "6543210";
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chars = strbits'(str);
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if(chars != "6543210")
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begin
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$display("FAILED 2 chars = %x", chars);
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$finish();
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end
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str = "wrong string";
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// Vector to string casting
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str = string'(chars);
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if(str != "6543210")
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begin
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$display("FAILED 3 str = %s", str);
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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