41 lines
722 B
Verilog
41 lines
722 B
Verilog
// Check that function calls within an assignment pattern are evaluated
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// correctly. The result should be the same as assigning the expression to a
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// variable with the same type as the base type of the assignment pattern
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// target.
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module test;
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int d[];
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int tmp;
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bit failed = 1'b0;
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`define check(expr) \
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d = '{expr}; \
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tmp = expr; \
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if (d[0] !== tmp) begin \
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$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", d[0], tmp); \
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failed = 1'b1; \
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end
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int x, y;
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function int fn(int x);
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return x*2;
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endfunction
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initial begin
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x = -3;
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y = 10;
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`check(fn(x))
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`check($clog2(y))
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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