46 lines
926 B
Verilog
46 lines
926 B
Verilog
// Check that the width of the element type of the target of an assignment
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// pattern is considered when evaluating the expression. The result should be
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// the same as assigning the expression to a variable with the same type as the
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// base type of the assignment pattern target.
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module test;
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int d[];
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int tmp;
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bit failed = 1'b0;
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`define check(expr) \
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d = '{expr}; \
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tmp = expr; \
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if (d[0] !== tmp) begin \
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$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", d[0], tmp); \
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failed = 1'b1; \
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end
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shortint x;
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bit [7:0] y;
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initial begin
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x = -11;
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y = 8'h80;
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// Sign extension
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`check(x)
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`check(16'sh8000)
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// No sign extension
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`check(8'hff)
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`check(y)
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// Gets evaluated in a 32 bit context, the result is 2/-2 not 0
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`check(1'b1 + 1'b1)
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`check(1'sb1 + 1'sb1)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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