35 lines
663 B
Verilog
35 lines
663 B
Verilog
// Check that concatenations are evaluated correctly in assignment patterns.
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// The result should be the same as assigning the expression to a variable with
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// the same type as the base type of the assignment pattern target.
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module test;
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int d[];
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int tmp;
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bit failed = 1'b0;
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`define check(expr) \
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d = '{expr}; \
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tmp = expr; \
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if (d[0] !== tmp) begin \
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$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", d[0], tmp); \
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failed = 1'b1; \
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end
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shortint x;
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byte y;
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initial begin
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x = -1;
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y = 10;
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`check({x,y})
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`check({3{y}})
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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