52 lines
1.0 KiB
Verilog
52 lines
1.0 KiB
Verilog
// Check that implicit cast works for expressions in assignment patterns. The
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// result should be the same as assigning the expression to a variable with the
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// same type as the base type of the assignment pattern target.
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module test;
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int dv[];
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real dr[];
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int tmpv;
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real tmpr;
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bit failed = 1'b0;
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`define check_v(expr) \
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dv = '{expr}; \
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tmpv = expr; \
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if (dv[0] !== tmpv) begin \
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$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", dv[0], tmpv); \
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failed = 1'b1; \
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end
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`define check_r(expr) \
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dr = '{expr}; \
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tmpr = expr; \
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if (dr[0] != tmpr) begin \
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$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", dr[0], tmpr); \
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failed = 1'b1; \
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end
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real r;
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int i;
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initial begin
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r = 4.56;
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i = -11;
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// Implicit cast from real to vector
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`check_v(1.234e16)
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`check_v(r)
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// Implicit cast from vector to real
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`check_r(32'hfffffff0)
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`check_r(i)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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