41 lines
1.2 KiB
Verilog
41 lines
1.2 KiB
Verilog
// This tests part selects of 2-value logic vectors through
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// module ports. This is not supported in SystemVerilog, but
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// we expect it to work as an Icarus Verilog extension, as
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// long as all the bits of the 2-value are singly driven.
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module main;
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bit [5:0] a, b;
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wire bit [6:0] sum;
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wire bit c2, c4;
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sub b10 (.c_i(1'b0), .a(a[1:0]), .b(b[1:0]), .out(sum[1:0]), .c_o(c2));
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sub b32 (.c_i(c2), .a(a[3:2]), .b(b[3:2]), .out(sum[3:2]), .c_o(c4));
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sub b54 (.c_i(c4), .a(a[5:4]), .b(b[5:4]), .out(sum[5:4]), .c_o(sum[6]));
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bit [6:0] idxa, idxb;
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initial begin
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for (idxa = 0 ; idxa < 'b1_000000 ; idxa = idxa+1) begin
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for (idxb = 0 ; idxb < 'b1_000000 ; idxb = idxb+1) begin
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a = idxa;
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b = idxb;
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#1 /* wait for devices to settle */;
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if (idxa + idxb != sum) begin
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$display("FAILED: %0d + %0d --> %0d", a, b, sum);
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$stop;
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end
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end
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end // for (idxa = 0 ; idxa < 'b1_000000 ; idxa = idxa+1)
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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module sub (input wire bit c_i, input wire bit[1:0] a, b,
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output wire bit [1:0] out, output wire bit c_o);
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assign {c_o, out} = {1'b0, a} + {1'b0, b} + {2'b00, c_i};
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endmodule // sub
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