47 lines
723 B
Verilog
47 lines
723 B
Verilog
// Check that the signedness of a struct member is handled correctly when passed
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// to a system function
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module test;
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bit failed = 1'b0;
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struct packed {
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int s;
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int unsigned u;
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} x;
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int s;
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int unsigned u;
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logic [16*8-1:0] s1;
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logic [16*8-1:0] s2;
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initial begin
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u = -10;
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s = -20;
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x.u = u;
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x.s = s;
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$swrite(s1, s);
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$swrite(s2, x.s);
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if (s1 != s2) begin
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failed = 1'b1;
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$display("FAILED. Expected %s, got %s.", s1, s2);
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end
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$swrite(s1, u);
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$swrite(s2, x.u);
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if (s1 != s2) begin
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failed = 1'b1;
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$display("FAILED. Expected %s, got %s.", s1, s2);
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end
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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