79 lines
1.7 KiB
Verilog
79 lines
1.7 KiB
Verilog
module main;
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typedef struct packed {
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logic [3:0] high;
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logic [3:0] low;
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} word;
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typedef word [1:0] dword;
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dword foo;
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int idx;
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initial begin
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foo[0].low = 1;
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foo[0].high = 2;
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foo[1].low = 3;
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foo[1].high = 4;
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$display("foo = %h", foo);
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if (foo !== 16'h4321) begin
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$display("FAILED -- foo=%h", foo);
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$finish;
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end
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$display("foo[0] = %h", foo[0]);
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if (foo[0] !== 8'h21) begin
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$display("FAILED -- foo[0]=%h", foo[0]);
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$finish;
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end
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$display("foo[1] = %h", foo[1]);
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if (foo[1] !== 8'h43) begin
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$display("FAILED -- foo[1]=%h", foo[1]);
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$finish;
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end
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$display("foo[0].low = %h", foo[0].low);
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if (foo[0].low !== 4'h1) begin
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$display("FAILED -- foo[0].low=%h", foo[0].low);
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$finish;
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end
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$display("foo[0].high = %h", foo[0].high);
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if (foo[0].high !== 4'h2) begin
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$display("FAILED -- foo[0].high=%h", foo[0].high);
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$finish;
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end
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$display("foo[1].low = %h", foo[1].low);
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if (foo[1].low !== 4'h3) begin
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$display("FAILED -- foo[1].low=%h", foo[1].low);
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$finish;
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end
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$display("foo[1].high = %h", foo[1].high);
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if (foo[1].high !== 4'h4) begin
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$display("FAILED -- foo[1].high=%h", foo[1].high);
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$finish;
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end
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idx = 0;
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$display("foo[idx=0].low = %h", foo[idx].low);
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if (foo[idx].low !== 4'h1) begin
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$display("FAILED -- foo[0].low=%h", foo[idx].low);
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$finish;
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end
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idx = 1;
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$display("foo[idx=1].high = %h", foo[idx].high);
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if (foo[idx].high !== 8'h4) begin
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$display("FAILED -- foo[1].high=%h", foo[idx].high);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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