32 lines
570 B
Verilog
32 lines
570 B
Verilog
module main;
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wire struct packed {
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logic m1;
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logic [7:0] m8;
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} foo;
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assign foo = {1'b1, 8'ha5};
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struct packed {
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logic [3:0] m4;
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logic [7:0] m8;
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} bar;
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initial begin
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#1 /* wait for logic to settle. */;
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bar.m8 <= foo.m8[7:0];
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bar.m4 <= foo.m8[7:4];
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#1 $display("bar8=%h, bar4=%h", bar.m8, bar.m4);
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if (bar.m8 !== 8'ha5) begin
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$display("FAILED");
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$finish;
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end
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if (bar.m4 !== 4'ha) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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