27 lines
583 B
Verilog
27 lines
583 B
Verilog
module main;
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struct packed {
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logic [7:0] high;
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logic [7:0] low;
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} word1, word2;
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initial begin
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word1 = 16'haa_55;
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if (word1.high !== 8'haa || word1.low !== 8'h55) begin
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$display("FAILED: word1 = %h, word1.high = %h, word1.low = %h",
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word1, word1.high, word1.low);
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$finish;
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end
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word2 = word1;
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if (word2.high !== 8'haa || word2.low !== 8'h55) begin
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$display("FAILED: word2 = %h, word2.high = %h, word2.low = %h",
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word1, word2.high, word2.low);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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