44 lines
681 B
Verilog
44 lines
681 B
Verilog
module test();
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string str;
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always @(str) begin
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$display("str = %s", str);
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end
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task automatic test_task(input integer delay, input string str1, input string str2);
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string str;
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fork
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begin
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@(str) $display("str%0d = %s", delay, str);
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@(str) $display("str%0d = %s", delay, str);
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end
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begin
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#delay;
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#2 str = str1;
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#2 str = str1;
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#2 str = str2;
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end
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join
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endtask
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initial begin
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#1 str = "hello";
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#1 str = "hello";
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#1 str = "world";
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fork
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test_task(1, "hello1", "world1");
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test_task(2, "hello2", "world2");
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join
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fork
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test_task(1, "world1", "hello1");
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test_task(2, "world2", "hello2");
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join
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#1 $finish(0);
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end
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endmodule
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