77 lines
2.0 KiB
Verilog
77 lines
2.0 KiB
Verilog
/*
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* Copyright (c) 2002 Tom Verbeure
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module main;
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integer myInt;
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reg [39:0] myReg40;
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reg [0:39] myReg40r;
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reg [0:38] myReg39r;
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reg [13:0] myReg14;
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reg [7:0] myReg8;
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initial begin
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$display("============================ myReg8 = 65");
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myReg8 = 65;
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$display(">|A|");
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$display("*|%s|", myReg8);
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$display("============================ myReg40 = \"12345\"");
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myReg40 = "12345";
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$display(">|12345|");
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$display("*|%s|", myReg40);
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$display(">|5|");
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$display("*|%s|", myReg40[7:0]);
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$display("============================ myReg40r = \"12345\"");
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myReg40r = "12345";
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$display(">|12345|");
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$display("*|%s|", myReg40r);
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$display(">|1|");
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$display("*|%s|", myReg40r[0:7]);
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$display("============================ myReg39r = \"12345\"");
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myReg39r = "12345";
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$display(">|12345|");
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$display("*|%s|", myReg39r);
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$display(">|b|");
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$display("*|%s|", myReg39r[0:7]);
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$display("============================ myReg14 = 65");
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myReg14 = 65;
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$display(">| A|");
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$display("*|%s|", myReg14);
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$display("============================ myReg14 = 33*356+65");
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myReg14 = 33*256 + 65;
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$display(">|!A|");
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$display("*|%s|", myReg14);
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$display("============================ myInt = 65");
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myInt = 65;
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$display(">| A|");
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$display("*|%s|", myInt);
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end
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endmodule
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