50 lines
1.5 KiB
Verilog
50 lines
1.5 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - assign a string in a function
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//
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// This test was contributed via forwarding on the geda netlist. I don't
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// know who actually wrote it - that isn't obvious from the copy of email
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// I eventually received - SDW
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//
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module test();
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wire [31:0] A;
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reg [31:0] B;
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function [31:0] message;
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input [1:0] reg_num;
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begin
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message = (reg_num == 2'b00) ? "Mes0":
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(reg_num == 2'b01) ? "Mes1":
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(reg_num == 2'b10) ? "Mes2":
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"Mes3";
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end
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endfunction
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assign A = "hi";
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initial
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begin
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B = "ho";
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#1;
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$display ("%s", A);
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$display ("%s", message(1));
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$finish(0);
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end
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endmodule
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