106 lines
1.6 KiB
Verilog
106 lines
1.6 KiB
Verilog
/*
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* In this example, the set and clr are both synchronous. This checks
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* that this complex case is handled correctly.
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*/
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module main;
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reg Q, clk, rst, set, clr;
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(* ivl_synthesis_on *)
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always@(posedge clk or posedge rst)
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begin
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if (rst)
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Q <= 1'b0;
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else if (set)
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Q <= 1'b1;
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else if (clr)
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Q <= 1'b0;
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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rst = 0;
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set = 0;
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clr = 0;
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#1 rst = 1;
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#1 rst = 0;
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if (Q !== 0) begin
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$display("FAILED -- rst");
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 0) begin
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$display("FAILED -- 1 clk");
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$finish;
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end
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#1 set = 1;
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#1 ;
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if (Q !== 0) begin
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$display("FAILED -- 1 set (no clk)");
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 1) begin
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$display("FAILED -- 1 set");
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$finish;
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end
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#1 clr = 1;
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#1 ;
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if (Q !== 1) begin
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$display("FAILED -- 1 clr+set (no clk)");
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 1) begin
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$display("FAILED -- 1 clr+set");
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 1) begin
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$display("FAILED -- 2 clr+set");
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$finish;
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end
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#1 set = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 0) begin
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$display("FAILED -- 1 clr-set");
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$finish;
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end
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#1 clr = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (Q !== 0) begin
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$display("FAILED -- 1 set-clr");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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