17 lines
490 B
Verilog
17 lines
490 B
Verilog
module top;
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reg [63:0] str;
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reg [31:0] in, ck, out;
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integer res;
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initial begin
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// To avoid embedded NULL bytes each byte must have a 1.
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in = 32'b000x100z_001z000x_101xxxzz_100z111x;
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ck = 32'b00001000_00100000_10100000_10001110;
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$sformat(str, "%u", in);
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res = $sscanf(str, "%u", out);
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if (res !== 1) $display("FAILED: $sscanf() returned %d", res);
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else if (ck !== out) $display("FAILED: %b !== %b", in, out);
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else $display("PASSED");
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end
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endmodule
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